1. Field of the Invention
The present invention relates generally to reducing memory and communication bandwidth requirements in Global Navigational Satellite System (GNSS) receivers and, more particularly, to reducing memory and communication bandwidth requirements for digital signal samples in GNSS receivers.
2. Description of the Related Art
Satellite navigational systems provide positional and timing information to earth-bound receivers. Each system has its own constellation of satellites orbiting the Earth, and, in order to calculate its position, a receiver on Earth uses the satellites “in view” (i.e., in the sky above) from that system's constellation. “Global Navigational Satellite Systems” (GNSS) is often used as the generic term for such systems, even though such navigational satellite systems include regional and augmented systems—i.e., systems that are not truly “global.” The term “GNSS,” as used herein, covers any type of navigational satellite system, global or not, unless expressly indicated otherwise.
GNSS systems, presently operational and planned, include the widely-known, widely-used, and truly global Global Positioning System (GPS) of the United States, Russia's GLObalnaya NAvigatsionnaya Sputnikovaya Sistema (GLONASS), Europe's Galileo and China's BeiDou (also known, in its second generation, as COMPASS) systems—each of which has, or will have, its own constellation of satellites orbiting the globe. Regional systems (those that are not global, but intended to cover only a certain region of the globe) include Japan's Quasi-Zenith Satellite System (QZSS) and the Indian Regional Navigational Satellite System (IRNSS) currently being developed. Augmented systems are normally regional as well, and “augment” existing GNSS systems with, e.g., messages from ground-based stations and/or additional navigational aids. These include the Wide Area Augmentation System (WAAS), European Geostationary Navigation Overlay Service (EGNOS), Multi-functional Satellite Augmentation System (MSAS), and GPS Aided Geo Augmented Navigation (GAGAN). Regional GNSS systems, such as QZSS, can also operate as augmented systems.
GNSS receiver architectures vary in detail depending on the specific implementation, as is well-known to one of ordinary skill in the art, but there are certain functions and/or components that must be addressed by any GNSS receiver. All GNSS receiver architectures have an antenna and a reception chain of components for taking the GNSS signals received by the antenna and shaping, filtering, amplifying, and down-converting the received signals from their received Radio Frequency (RF) to an Intermediate Frequency (IF), which is better for further processing. All of this typically occurs in the analog domain, and the last stage in the reception chain is the conversion from the analog signal to a digital signal and it is this digital signal which is further processed to extract the GNSS signal information.
Several types of GNSS receiver architectures temporarily store and/or forward, over a communication channel, the GNSS signals after they have been digitized. Three such architectures are described below, in reference to FIGS. 1-3, where the GNSS receiver architecture in FIG. 1 is a simple sample-and-store memory, the GNSS receiver architecture in FIG. 2 has a circular memory buffer, and the GNSS receiver architecture in FIG. 3 transmits the digital signal over a communications channel for further processing at a remote location (remote, that is, from the GNSS receiver architecture). FIGS. 1-3 are only examples of the types of receiver architectures, and specific implementations in GNSS receivers may include features of two or more of the architectures shown in FIGS. 1-3, as would be known to one of ordinary skill in the art.
In FIG. 1, antenna 110 in GNSS receiver 100 receives the GNSS signal, which is then processed by reception chain (RX) 120. Analog-to-Digital Converter (ADC) 130 takes the processed analog GNSS signal and converts it to a digital signal, where each digital sample output has N bits. In FIG. 1, the time interval for each sample is one (1) second, and each 1-second N-bit sample is stored in memory 150, where they are available to microprocessor 160 for further processing. Microprocessor 160 processes the digital samples from memory 150 to produce a navigation and timing solution.
In the circular memory buffer architecture shown in FIG. 2, antenna 210 in GNSS receiver 200 receives the GNSS signal, which is then processed by reception chain (RX) 220. Analog-to-Digital Converter (ADC) 230 takes the processed analog GNSS signal and converts it to a digital signal, where each digital sample output has N bits. By contrast with FIG. 1, the digital samples output by ADC 230 in FIG. 2 are input to a sample pre-processing module 240, which processes them into M-bit samples, each of which is of K msecs duration. These K msec M-bit samples are stored in memory 250, and then forwarded to sample post-processing module 245, which outputs the post-processed samples to microprocessor 260 at an accelerated clock rate. Microprocessor 260 processes the post-processed digital samples to produce a navigation and timing solution.
In the architecture shown in FIG. 3 which transmits digital signal samples over a communication channel, antenna 310 in GNSS receiver 300 receives the GNSS signal, which is then processed by reception chain (RX) 320. Analog-to-Digital Converter (ADC) 330 takes the processed analog GNSS signal and converts it to a digital signal, where each digital sample output has N bits. Each output N-bit digital signal sample is stored in memory 350, which is typically sized at several kilobytes. In FIG. 3, the digital samples stored in memory 350 are transmitted over a communication channel to a remote processing unit 360, which processes the received digital samples to produce a navigation and timing solution. This type of architecture can be used when the GNSS receiver 300 is not suitable for computation-intensive signal processing, which is better performed at a computer processing location. In some versions of this architecture, the digital samples are further processed before being transmitted over the communication channel.
In the archetype GNSS receiver architectures shown in FIGS. 1-3, as well as all other GNSS receiver architectures, resources including, without limitation, power, space, and circuitry, are required to store the digital samples in memory before processing by the microprocessor. In the GNSS architecture of FIG. 3, those resources include the transmit power, timing, and circuitry, as well as the bandwidth for transmitting the digital samples to the remote processing unit 360. Such resources are at a premium, especially when the GNSS receiver is in a portable device, such as a cellular phone, a tablet or laptop computer, a portable navigational device (such as a GPS receiver), or any of the myriad of portable personal consumer electronic devices which include any type of GNSS signal processing capability. The term “portable device” as used herein, covers any such implementation of GNSS capabilities in a device or system.
Because portable devices run on battery power at least a part of the time, any use of power, such as for memory storage and/or transmitting communication signals, is a drain. Moreover, to remain portable, portable devices must keep their internal circuitry to a minimum, and in GNSS receivers, a substantial portion of the silicon area is used just for memory.
Thus, there is a need, such as when a GNSS receiver is implemented in a portable device, which runs on battery power at least a part of the time, and may have limited interior space for circuitry, to minimize the resources needed for GNSS signal digital sample storage and/or transmission.